The present invention relates to an apparatus and method for increasing microelectronic device density. The invention has particular utility in connection with producing low-profile microelectronic device assemblies.
Semiconductor dies are commonly manufactured as part of a large wafer, then singulated. To withstand the rigors of processing and polishing, such wafers are typically on the order of 20-30 mils (about 500-760 xcexcm), with larger wafers tending to be thicker. With today""s larger wafer diameters, most conventional semiconductor dies have a thickness in excess of 25 mils (about 635 xcexcm), e.g., about 28 mils (about 710 xcexcm) for 300 mm diameter wafers. Increasingly, however, microelectronic device designs are calling for thinner dies. Using a thinner die yields a microelectronic device assembly having a lower profile, occupying less space. Sometimes, thinned dies are stacked vertically atop one another to further increase die density, preserving valuable substrate real estate. The upper die is commonly attached to the lower die then electrically coupled to the substrate.
Thinner semiconductor dies are commonly formed by grinding the back surface of a thicker wafer before slicing the wafer to produce a number of thinned, singulated dies. To protect electrical contacts and other features, the active surface of the thicker wafer is commonly coated with a protective coating, e.g., a layer of a polyimide. The unprotected back surfaces of the wafers may then be ground using chemical-mechanical or mechanical planarizing tools. Many of these protective coatings tend to shrink after they cure. This places the coated active surface of the die in compression while placing the exposed back surface of the die in tension. At its initial thickness of more than 25 mils, the wafer is typically stiff enough to withstand these forces. As the wafer become progressively thinner during grinding, however, the stress caused by the protective coating tends to warp the wafer. This warpage becomes more pronounced as conventional wafer sizes are increased from 200 mm diameters to diameters of 300 mm or more.
Warped wafers lead to significant product losses. First, the wafers are conventionally attached to dicing tape before the dies are singulated. This requires warped wafers to be pressed flat to provide uniform contact of the wafer surface with the dicing tape. The entire wafer may be damaged under the forces necessary to flatten the wafer against the dicing tape. Even after the previously warped wafer has been singulated into individual dies, the individual dies may still be warped. This makes it more difficult for automated handling machinery to pick up the individual dies with the required accuracy and precision. The residual stress in the warped dies also weakens the die, making it easier to propagate small cracks through the die. As a consequence, dies which survive the wafer thinning and singulation process may be damaged while assembling microelectronic device assemblies, leading to higher losses of the final, higher-value assembled devices.
To minimize unacceptable product losses due to wafer warping, the minimum wafer thickness deemed practical in a commercial environment is on the order of 10-12 mils (about 250-305 xcexcm). In most semiconductor dies, the active features of the die are located within 20 xcexcm or less of the active surface of the die. Conventional handling and processing equipment, therefore, places a practical limit on the thickness of semiconductor dies which is 10-15 times as thick as that necessary to provide a die with the requisite active features.
In U.S. Pat. No. 5,273,940, the entirety of which is incorporated herein by reference, Sanders proposes a multiple-chip package with thinned semiconductor chips. A number of chips are mounted on a surface of a substrate and encapsulation material is placed on the surface of the substrate around the semiconductor chips. A grinding wheel is then used to grind down both the semiconductor chips and the encapsulation material to a desired thickness. Sanders claims that this process can reduce a semiconductor chip from an initial thickness of about 20 mils (508 xcexcm) to 4.5-5 mils (114.3-127 xcexcm).
Sanders claims to yield semiconductor chips which are significantly thinner than those which can be handled reliably in a commercial production environment, but the presence of the encapsulation material on the surface of the substrate limits the utility of this approach. As noted above, semiconductor dies are frequently stacked vertically atop one another to increase die density on the substrate. Because Sanders"" encapsulation material covers the surface of the substrate, additional dies stacked on the thinned dies cannot be electrically coupled to the substrate directly using conventional wire bonding. Grinding the exposed surfaces of the semiconductor chips would also grind away active features provided on the back surface of the chips. As a consequence, Sanders provides no mechanism for electrically coupling a second chip to the upper surface of the thinned chips on the substrate. As a result, Sanders does not propose a mechanism for manufacturing microelectronic device assemblies with stacked dies.
Embodiments of the present invention provide low-profile microelectronic device assemblies and methods for manufacturing such microelectronic device assemblies. One embodiment of the invention provides a method of assembling a stacked microelectronic device assembly from a microelectronic device sub-assembly. The sub-assembly may include a support having a first electrical contact and a first die attached to and electrically coupled to the support. In accordance with this method, the first die of the microelectronic device sub-assembly is mechanically thinned while the first electrical contact is exposed. This may be accomplished by grinding a back surface of the first die. Thereafter, a second die may be connected to the first die and the second die may be electrically coupled to the exposed first electrical contact.
A method in accordance with an alternative embodiment of the invention reduces the thickness of a microelectronic device assembly which includes a support and a first die, the first die being electrically coupled to the support and attached to a mounting surface of the support. In accordance with this method, an exposed back surface of the first die is ground with the mounting surface of the support partially exposed. This reduces the thickness of the first die. If so desired, a second die may be connected to the first die and this second die may be electrically coupled to the support.
Another embodiment of the invention provides a method of assembling a microelectronic device assembly. In accordance with this method, a first die is connected to a support. An underfill gap is defined between an active surface of the first die and a mounting surface of a support. This gap can be filled with an underfill material, leaving a portion of the mounting surface exposed. Thereafter, the thickness of the first die is reduced, e.g., by grinding a back surface of the first die. If so desired, a second die may then be connected to the first die.
Another embodiment of the invention provides a method of assembling a microelectronic device assembly which includes a support, a first die, and a second die. The support has a mounting surface, a first contact and a second contact. The first die may have an active surface bearing a third contact and the second die may have a fourth contact. The active surface of the first die is mechanically supported with respect to the mounting surface of the support. The first contact of the support is electrically coupled to the third contact of the fist die. The thickness of the first die is reduced, such as by grinding a back surface of the die. Thereafter, the second die is connected to the first die and the second contact of the substrate may be electrically coupled to the fourth contact of the second die. The first die may be mechanically supported with respect to the support by introducing a mechanically stable material in a gap between the active surface and the mounting surface.
Still another embodiment of the invention provides a method of assembling a stacked microelectronic device assembly from a microelectronic device sub-assembly. This microelectronic device sub-assembly includes a support and a first die attached to and electrically coupled to the support. An exposed back surface of the first die is ground, thereby reducing the thickness of the first die. Thereafter, a redistribution layer is attached to the ground back surface of the first die. A second die is connected to the redistribution layer and electrically coupled to the first die via the redistribution layer.
A microelectronic device assembly in accordance with another embodiment of the invention comprises a support including a partially exposed mounting surface and a first electrical contact. A first die having a thickness of no greater than 4 mils has an active surface having a second electrical contact. The active surface of the first die faces and is mounted on the mounting surface of the support and the first electrical contact is coupled to the second electrical contact.
A microelectronic device assembly in accordance with a further embodiment of the invention comprises a support, a first die and a second die. The support includes a mounting surface, a first electrical contact, and a second electrical contact. The first die has a thickness of no more than 4 mils. The first die includes a ground back surface and an active surface having a third electrical contact. The active surface of the first die faces and is mounted on the mounting surface of the support. The first electrical contact is coupled to the second electrical contact. The second die is carried by the ground back surface of the first die. The second die is electrically coupled to the second electrical contact of the support.
Yet another embodiment of the invention provides a microelectronic device assembly which includes a support, a first die, a second die and an intermediate layer. The support includes a mounting surface and a first electrical contact. The first die has a thickness of no more than 4 mils and includes a ground back surface having an electrical element and an active surface having a second electrical contact. The active surface of the first die may face and be mounted on the mounting surface of the support and the first electrical contact may be coupled to the second electrical contact. The second die has a third contact carried on a facing surface. The intermediate layer may be disposed between the ground back surface of the first die and the facing surface of the second die. The intermediate layer can be electrically coupled to the electrical element of the first die and to the third contact of the second die.